Comparison of Gate Sizing Formulations and Solving Methods

Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We introduce a sizable model for CMOS gates. Using this model we describe a gate sizing formulation for CMOS circuits. This model contains linear and some nonlinear equations. We solve the gate sizing formulation with three linear programming solvers for which we linearize the nonlinear equations. We also solve the gate sizing problem with a geometric and a general nonlinear programming solver. We present results for the five solvers for circuits up to a several thousand gates. We also discuss the advantages and disadvantages of each solver for the purpose of gate sizing.